資料來源 : Free On-Line Dictionary of Computing

Intersil 6100
     
         (IMS 6100) A single chip design of the {DEC}
        {PDP-8} {minicomputer}.  The old PDP-8 design was very
        strange, and if it hadn't been popular, an awkward {CPU} like
        the 6100 would never been designed.
     
        The 6100 was a 12-bit processor, which had three {registers}:
        the {PC}, AC (accumulator), and MQ.  All 2-operand
        instructions read AC and MQ and wrote back to AC.  It had a
        12-bit {address bus}, limiting {RAM} to only 4K.  Memory
        references were 7-bit, offset either from address 0, or from
        the PC page base address (PC AND 7600 oct).
     
        It had no {stack}.  Subroutines stored the {PC} in the first
        word of the subroutine code itself, so {recursion} required
        fancy programming.
     
        4K RAM was pretty much hopeless for general purpose use.  The
        6102 support chip (included in the 6120) added 3 address
        lines, expanding memory to 32K the same way that the PDP-8/E
        expanded the PDP-8.  Two registers, IFR and DFR, held the page
        for instructions and data respectively (IFR was always used
        until a data address was detected).  At the top of the 4K
        page, the PC wrapped back to 0, so the last instruction on a
        page had to load a new value into the IFR if execution was to
        continue.
     
        (2003-04-04)