資料來源 : Free On-Line Dictionary of Computing

delayed control-transfer
     
         A technique used on the {SPARC} to reduce
        the effect of {pipeline breaks} by executing the instruction
        after a branch instruction (the "delay instruction" in the
        "delay slot").  If there is no useful instruction which can be
        placed in the delay slot then the "annul bit" on the control
        transfer instruction can be set, preventing execution of the
        delay instruction (unless the control transfer is conditional
        and is taken).
     
        Annulled branches are indicated in SPARC assembler language by
        appending ",A" to the {operation code}.  For example,
     
         LOOP: ...
         CMP    %L0,10
         BLE,A   LOOP
         ADD     %L2, %L3, #L4
     
        If the delay instruction is also a control transfer
        instruction then it gets more complicated.  Both control
        transfer instructions are executed (but not the following
        instruction) and, assuming they are both taken, control is
        transferred briefly to the destination of the first and then
        immediately to the destination of the second.
     
        (2001-06-26)